1. Field of the Invention
The invention relates to a semiconductor integrated circuit, and more particularly, to a delay locked-loop circuit for reducing the load of a variable delay unit at high frequency operation and stably locking an external clock signal.
2. Description of the Related Art
Synchronous DRAMs synchronize with a clock signal to input and output data to and from memory cells. The clock signal is typically input via a single input pin and then distributed to the synchronous DRAMs. A clock signal reaching a point relatively far from the input pin may be considerably delayed compared to a clock signal reaching a point adjacent to the input pin. This delay disrupts the synchronization of each component in a synchronous DRAM.
Delay locked-loop circuits are typically used to maintain synchronization and generate an internal clock signal synchronized with an external clock signal. A delay locked-loop circuit operates at almost the same speed as the operation speed of a synchronous DRAM. A delay locked-loop circuit must operate at or above a predetermined frequency (hereinafter, referred to as high-frequency operation) and at or below the predetermined frequency (hereinafter, referred to as low-frequency operation).
FIG. 1 shows a typical delay locked-loop circuit. A delay locked-loop circuit 100 comprises a phase detector 110, a delay unit controller 120, and a variable delay unit 130. The phase detector 110 detects a phase difference between an external clock signal ECLK and an internal clock signal ICLK. The delay unit controller 120 generates a control signal CNT that controls the delay time of the external clock signal ECLK input into the variable delay unit 130 in response to output of the phase detector 110. The variable delay unit 130 generates an internal clock signal ICLK that is synchronized with the external clock signal ECLK in response to the control signal CNT.
FIG. 2 shows the variable delay unit 130 shown in FIG. 1. The variable delay unit 130 comprises delay cells 201 through 208 and switch transistors 211 through 218. The delay cells 201 through 208 are each connected to one of the switch transistors 211 through 218, which are connected to an output line OL1 of the variable delay unit 130. The delay cells 201 through 208 delay the external clock signal ECLK.
The number of the delay cells 201 through 208 depends on the operation frequency of the delay locked-loop circuit 100. The number of delay cells 201 through 208 for high-frequency operation will be less than that for low-frequency operation. In the case of low-frequency operation, the switch transistors 211 through 218 are all turned on in response to the control signal CNT to connect the delay cells 201 through 208 to the output line OL1. Thus, the load of the output line OL1 is high. In the case of high-frequency operation, transistors 215 through 218 are not turned on and delay cells 205 through 208 do not affect the output line OL1, therefore the load of the output line OL1 is small.
The variable delay unit 130 has a line load proportional to the physical length of the output line OL1 and a junction load due to the switch transistors 211 through 218, which are turned off, even if the delay cells 205 through 208 are not connected to the output line OL1 for high-frequency operation. Thus, the variable delay unit 130 is inappropriate in the case of high-frequency operation. As a result, jitter is apparent in the internal clock signal ICLK that is generated in the delay locked-loop circuit 100 shown in FIG. 1 and a duty ratio becomes degraded. Thus, the synchronous DRAM does not operate properly.